Conventional integrated circuit dice 101A-101N (a total of N dice) included in semiconductor substrate 100 (see FIG. 1A) are fabricated by forming patterns (not shown) in conductive and insulative layers (e.g. layer 130 in FIG. 1D). Depending on the complexity of the fabrication process, the number of such layers can range from ten to more than thirty. During the fabrication process, a pattern in a layer (e.g. layer 130) being formed is aligned to a pattern in a previously formed layer, to ensure isolation or interconnection (as appropriate) of various parts of electronic devices (not shown) being formed in dice 101A-101N.
Alignment between patterns in different layers is typically performed in a tool called a "stepper". The stepper aligns patterns by use of a laser beam (not shown) to sense the position of two alignment marks 121I (FIG. 1A) and 121J formed in substrate 100. Alignment marks 121I and 121J (only one mark 121J is illustrated in FIG. 1B) are formed at the bottom of corresponding openings (known as "windows") 120I and 120J in fields 102I and 102J. Fields 102I and 102J are portions of substrate 100 that are skipped by the stepper while forming patterns for electronic devices in certain areas, called "active areas" that correspond to dice 101A-101N and that are formed in most of the area of substrate 100.
Alignment marks 121I and 121J typically include a number of stripes, formed at the bottom of a window. For example, alignment mark 121J (FIG. 1C) includes a number of low stripes 121A-121D, and a number of high stripes 121X-121Z interleaved between low stripes 121A-121D. The dimensions and geometry of alignment marks 121I, 121J depend on the specific model of the stepper being used. For example, a stepper ASM 2500/40 available from ASM Lithography, Veldhoven, The Netherlands, requires the stripe height Sh to be approximately 1.2 K.ANG..+-.0.4 K.ANG. to ensure proper detection of alignment marks. In this example, stripes 121A-121D and 121X-121Z are formed by etching to a depth (equal to a stripe's height) Sh, for example 1.5 K.ANG., into substrate 100. Stripes 121X-121Z have a width Sw of, for example, 8 .mu.m (80 K.ANG.), and are horizontally separated from each other by the same width Sw. Window 120J has an area (called "window area") of, for example, 1 mm.times.1 mm and a depth Wd, for example in the range of 5-10 K.ANG. (estimated depth). Therefore an upper surface 100U of substrate 100 is separated from a bottom surface 100B by depth Wd.
Although only three high stripes 121X-121Z (and four low stripes 121A-121D) are illustrated in FIGS. 1C-1F, typically there are several groups of such high stripes (e.g. four groups) in an alignment mark. Stripes in a group are typically identical to each other, but may have different dimensions and orientation from stripes in another group.
After creation, if an alignment mark 121J is buried, for example, underneath oxide layer 130 (FIG. 1D), another alignment mark 131J is typically formed on. oxide layer 130 by replication of buried alignment mark 121J. However global planarization, such as chemical mechanical polishing, can destroy the replicated alignment mark 131J. For example, if oxide layer 130 is globally planarized, alignment mark 131J (FIG. 1D) on exposed surface 130E of oxide layer 130 is destroyed, because a polished surface 130S (FIG. 1E) of substrate 100 becomes substantially flat, devoid of alignment mark 131J. Such loss of alignment marks 131I (not shown) and 131J (FIG. 1D) limits the number of layers that can be formed after chemical mechanical polishing, unless a buried alignment mark (e.g. alignment mark 121J) underneath oxide layer 130 is recovered. Buried alignment marks are usually recovered by a separate step, for example by etching oxide layer 130 (FIG. 1F) in window area 130W (FIG. 1E) bounded by window 120J.
U.S. Pat. No. 5,401,691 by Caldwell that is incorporated by reference herein in its entirety describes a method in which a "first insulating layer is . . . chemically-mechanically polished so that the alignment mark is not replicated" (col. 3, lines 64-66) and also a "second insulating layer is . . . chemically-mechanically planarized such that the alignment mark is not replicated . . . " (col. 4, lines 15-18). Caldwell requires repeated recovery of alignment marks that are lost during planarization. Specifically, Caldwell requires "contact etch that! uncovers and recaptures alignment mark 310 formed in polysilicon layer 320" (col. 9, lines 3-7). Caldwell also teaches that after "alignment mark 310 is replicated in metal 1 layer 332" (col. 9, lines 26-27), "d!uring via etch, ILD inter-layer-dielectric! 336 over alignment mark area 308 is simultaneously etched to recover and reveal alignment mark 310 formed in metal layer 332" (col. 10, lines 14-17).
Caldwell also requires processing (e.g. etching of polysilicon layer and etching of metal layer) in a "dropout area" "s!urrounding and directly adjacent" to an alignment mark (col. 3, lines 51-53). For example, Caldwell states that "b!y removing layers . . . from dropout area 306, the surface topography of dropout area 306 is consistently below the topography of other substrate areas during processing" (col. 10, lines 48-52).